A conventional data processing system includes a main memory, a Central Processing Unit (CPU) and a peripheral device (e.g., an input/output device or a peripheral memory). In such a data processing system, information (data) is transferred under the control of the CPU which executes a transfer operation according to a program stored therein.
In order to improve system performance of the conventional data processing system, it is known to employ a Direct Memory Access (DMA) controller, thereby forming a so-called DMA data-processing system which improves system performance by executing data transfers between the main memory and the peripheral unit without the use of the CPU. In a DMA data processing system, data is transferred in data blocks from a source device to an area of a destination device so that the data transfer can be effected at a high speed. A data block refers to data items (e.g., bytes) stored in a plurality of consecutive address or storage locations. The general process of a DMA data processing system will now be described.
When a block data transfer is to be performed, the peripheral unit of the DMA processing system sends to the DMA controller a "request" signal requesting the execution of a block data transfer from or to the main memory. After receiving the request signal, the DMA controller sends a "hold" request signal to the CPU. The CPU determines, after each instruction cycle, whether the hold request signal has been sent by the DMA controller. Upon determining that the hold request signal has been sent, the CPU relinquishes control of the system buses to the DMA controller which can then directly transfer a data block between the main memory and the peripheral device. Once the block data transfer is completed, the DMA controller relinquishes control of the system buses back to the CPU.
U.S. Pat. Nos. 4,271,466, 4,346,439, 4,471,427, 4,542,457 and 4,545,014 are examples of known direct memory access data processing systems. These cited patents, which are expressly incorporated herein by reference, provide a background understanding of direct memory access data processing systems.
In direct memory access control systems, before a DMA controller can directly transfer a data block from the source device to a destination device (e.g., a memory), the DMA controller must align the source device addresses or storage locations which contain the data block with the addresses or storage locations of the destination device. More specifically, before the data block can be transferred to the destination device, the starting address of the source device (i.e., the starting address of the data block) must be aligned with the specified starting address of the destination device. This technique is known as boundary alignment. Odd boundary alignment refers to the situation in which, for example, the position of the starting address of the source device relative to a data word location which contains the starting address does not correspond to the same position of the starting address of the destination device relative to the destination device data word which contains the starting address. For example, consider two memories, each consisting of a plurality of double data-words (i.e., four consecutive (8-bit) bytes). The address 61 (HEX) corresponds to the "second" byte of the double word consisting of data addresses 60-63 (HEX). The address 83 (HEX) corresponds to the "fourth" or "last" byte of the double word consisting of data addresses 80-83. If the starting address of the source device is 61 and the starting address of the destination device is 83, then there would be odd boundary alignment because data address 61 (which corresponds to the second position of the double word 60-63) is being transferred to address 83 of the destination device (which corresponds to the fourth or last position of the double word 80-83).
IBM Technical Disclosure Bulletin, December, 1984, pp. 4247-4248 discloses a shifter network that is used in a DMA mode of operation to perform memory-to-memory transfers on odd boundary addresses from a master device to a slave device. The shifter network consists of three registers of four bytes each. The first register communicates with the master, and the third register communicates with the slave. Data from the master is loaded into the shifter network and is shifted up or down by the amount of address misalignment or mismatch with the slave. The resulting aligned data is then transferred to the slave via the third register. Any data left in the shifter network is sent to the third register in inverted format, and then more data is loaded from the master. The data is then shifted by the number of bytes now stored in the third register such that the third register subsequently transfers a full word of data.
Although this reference discloses a system for aligning data on odd address boundaries, it does not consider data transfers by a DMA controller between source and destination devices which are smaller than the DMA controller (i.e., a DMA controller which has a 32-bit bus width and which performs a data transfer between 16-bit or 8-bit size source/destination devices). Further, the system is somewhat complicated since it requires that data remaining in the shifter network, after a transfer step, be inverted, and sent to another register.